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ROCCC 2.0

Riverside Optimizing Compiler for Configurable Computing (ROCCC) 2.0 features:

An open source C-to-VHDL compiler infrastructure tool that builds upon the experience gained from the ROCCC toolset. It is designed for the development of code accelerators that are mapped to FPGAs. ROCCC 2.0 maintains all the extensive compiler optimizations developed in ROCCC (e.g. data re-use through smart buffers, systolic array generation and general loop and procedure levels optimizations). It introduces two novel features that simplify the design of hardware code accelerators: modular bottom-up designs and platform interface abstractions.

• Modular bottom-up design. Allows a user to build-up an accelerator design with Lego-like construction using modules providing a structure for code reuse:

  • The code of a module is a fully functional C code that is compiled to VHDL by ROCCC 2.0

  • A module can import other modules in C, VHDL or as a netlist or IP core.

  • Modules available to a user are maintained in a database.

• Platform Interface Abstraction (PIA) decouples the specifics of a particular platform from the code generated by ROCCC.