ROCCC related publications
- R. Halstead, J. Villarreal,
R. Moussalli and W. A. Najjar. Is There A Tradeoff
Between Programmability and Performance?In 2010 Asilomar Conference
on Signals, Systems, & Computers, Asilomar, CA,
November 2010. (DOI:
dx.doi.org/10.1109/ACSSC.2010.5757683). [PDF]
- J. Villarreal, A. Park, R.
Atadero, W. A. Najjar and G. Edwards. Programming the
Convey HC-1 with ROCCC 2.0 in The
First Workshop on the Intersections of Computer
Architecture and Reconfigurable Logic (CARL 2010),
Atlanta, Georgia, December 5, 2010. Co-located with
MICRO-43. [PDF]
- A. B. Buyukkurt, J.
Villarreal, W. A. Najjar. Impact of High Level
Transformations within the ROCCC Framework. In ACM Trans. on
Architecture and Code Optimization, 7, 4, Article 7
(December 2010). [PDF]
- J. Villarreal, A. Park, W.
A. Najjar and R. Halstead. Designing Modular
Hardware Accelerators in C With ROCCC 2.0, in The 18th An. Int. IEEE
Symp. on Field-Programmable Custom Computing Machines
(FCCM), Charlotte, NC, May 2010. [PDF]
- W. A. Najjar and J.
Villarreal. Modular Design of FPGA-Based
Accelerators in C, Military and Aerospace
Programmable Logic Devices (MAPLD), NASA Goddard
Space Flight Center, Greenbelt, MD, August 2009.
- W.
A. Najjar and J. Villarreal. Reconfigurable Computing in
the New Age of Parallelism. SAMOS Workshop,
July 2009. [PDF]
- J. Villarreal and W. A. Najjar. Compiled Hardware
Acceleration of Molecular Dynamics Code, in
Int. Conf. on Field Programmable Logic and
Applications (FPL 08), Heidelberg, Germany,
September 2008 [PDF].
- A. B. Buyukkur and W. A. Najjar. Compiler Generated Systolic
Arrays For Wavefront Algorithm Acceleration on
FPGAs, in Int. Conf. on Field Programmable
Logic and Applications (FPL 08), Heidelberg,
Germany, September 2008. [PDF]
- M. Wirthlin, D. Poznanovic, P.
Sundararajan, A. Coppola, D. Pellerin, W. A. Najjar,
R. Bruce, M. Babst, O. Prichard, P. Palazzari and G.
Kuzmanov. OpenFPGA CoreLib Core Library
Interoperability Effort, in Parallel
Computing, Vol. 34, No. 4, pp. 231-244, Elsevier. [PDF]
- Z. Guo, A. B. Buyukkurt, J. Cortes, A.
Mitra, W. A. Najjar. A Compiler Intermediate
Representation for Reconfigurable Fabrics in Int.
Journal of Parallel Programming (IJPP), Springer
(http://www.springerlink.com/content/u124q758h231414k/).
[PDF]
- Z. Guo, W. A. Najjar, A. B. Buyukkurt. Efficient Hardware Code
Generation for FPGAs, in ACM Trans. on
Architecture and Compiler Optimizations (TACO) Vol.
5, No. 1, Article 6, May 2008, 26 pages, ACM. [PDF]
- J. Villarreal, J. Cortes,
and W. A. Najjar, Compiled Code
Acceleration of NAMD on FPGAs, in Reconfigurable Systems
Summer Institute, Urbana, IL, July 2007. [PDF]
- Z. Guo, A. Mitra
and W. A. Najjar. Automation of IP Core
Interface Generation for Reconfigurable Computing,
in 16th Int. Conf. on Field Programmable Logic and
Applications (FPL 2006), Madrid, Spain, August 2006.
[PDF]
- Z. Guo and W. A. Najjar. A Compiler Intermediate
Representation for Reconfigurable Fabrics, in
16th Int. Conf. on Field Programmable Logic and
Applications (FPL 2006), Madrid, Spain, August 2006.
[PDF]
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